Introduction to DMA content
Key Features of DMA
– Each channel is directly connected to a dedicated hardware DMA request and each channel also supports software configured software triggers.
– The priority between multiple requests on the same DMA module can be set programmatically via software (there are four levels: very high, high, medium and low) and the hardware determines when the priority settings are equal (the request has 0) . a higher priority value than request 1, etc.).
– Transmission width (byte, half-word, whole-word) of independent source and destination data areas, simulating the compression and decompression process. The source and destination addresses must be aligned according to the data transfer width.
– Circular buffer management support.
– Each channel has 3 event flags (DMA Transmit Midway, DMA Transmit Complete, and DMA Transmit Error) that logically become a single abort request.
– Memory-to-memory, device-to-memory, and memory-to-device transfers.
– Flash memory, SRAM, SRAM peripheral devices, APB1, APB2 and AHB can be used as access source and access target.
– Programmable number of data transfers: maximum 65535 (0xFFFF).
DMA controller for the STM32F411x chip family
The block diagram of the DMA process is shown in the figure below. The DMA controller shares the system data bus with the Cortex™-M4 core and performs direct data transfer to memory. If the CPU and DMA access the same target (RAM or peripherals) at the same time, the DMA request maintains CPU access to the system bus for multiple cycles, and the bus arbiter performs round-robin scheduling to ensure at least half of the system bus bandwidth (memory or peripherals) is available to the processor.
DMA controller transfer acts as an AHB master that supports direct memory and can control the AHB bus control matrix to initiate AHB transfers. It can carry out the following exchange of information:
– storage devices.
– Memory for device
– memory by heart
The DMA controller provides two main AHB ports: the memory AHB port (for memory connections) and the peripheral AHB port (for peripheral connections). However, to allow memory-to-memory transfers, the peripheral port AHB must also have access to memory. The AHB slave port is used for software control of the DMA controller (only 32-bit access is supported).